1. Field of the Invention
The present invention relates to a circuit for generating a reference voltage at a prescribed voltage level in a semiconductor device, and more particularly to a reference voltage generating circuit capable of generating a reference voltage exhibiting an extremely small dependency on power supply voltage and operating temperature.
2. Description of the Background Art
In a semiconductor integrated circuit, a reference voltage at a constant voltage level independent of an external or internal power supply voltage is required, for example, in the following case. To realize a circuit integrated with higher density, semiconductor elements being components thereof are downscaled. The breakdown voltage of such miniaturized semiconductor element is lowered, and thus, the power supply voltage (operating power supply voltage) of the semiconductor integrated circuit having those miniaturized semiconductor elements as its components need to be lowered. Practically, however, the external power supply voltage cannot always be lowered. In the case of a DRAM (dynamic random access memory) having a large storage capacity, for example, the power supply voltage (operating power supply voltage) is lowered from the standpoints of breakdown voltage, operating speed and power dissipation of elements. However, components of external devices such as a microprocessor and a logic LSI have not been miniaturized to the extent of those of DRAM, and therefore, their power supply voltages cannot be lowered to the level of that of DRAM. Consequently, when a system using a DRAM, a microprocessor and others is to be formed, a power supply voltage at a high voltage level that is required by the microprocessor, logic LSI and so on is used as a system power supply.
When the system power supply or the external power supply voltage is relatively high, a semiconductor device requiring a low operating power supply voltage, such as a DRAM, is provided with a circuit for internally down-converting the external power supply voltage to generate an internal power supply voltage.
FIG. 29 is a diagram schematically showing the entire configuration of a semiconductor device, e.g., a DRAM, incorporating such internal voltage down converter. Referring to FIG. 29, the semiconductor device 900 includes: an external power supply line 902 for transmitting an external power supply voltage EXV supplied to a power supply terminal 901; another power supply line (hereinafter, referred to as a ground line) 904 for transmitting the other power supply voltage (hereinafter, referred to as a ground voltage) Vss supplied to the other power supply node (hereinafter, referred to as a ground node) 903; and an internal voltage down converter 905 that operates using voltages EXV and Vss on external power supply line 902 and on ground line 904, respectively, as both operating power supply voltages, for down-converting external power supply voltage EXV to generate an internal power supply voltage VCI on an internal power supply line 906. This voltage down converter 905, of which a configuration will be described later, has a function to generate a stable internal power supply voltage VCI within a certain range of external power supply voltage EXV, independent of its fluctuation.
Semiconductor device 900 further includes: an internal power supply utilizing circuit 907 that operates using voltages VCI and Vss on internal power supply line 906 and ground line 904, respectively, as both operating power supply voltages; and an external power supply utilizing circuit 908 that operates using external power supply voltage EXV on external power supply line 902 and ground voltage Vss on ground line 904 as both operating power supply voltages. External power supply utilizing circuit 908 is connected to an input/output terminal 909 and has a function to interface with an external device. By generating internal power supply voltage VCI at a prescribed voltage level within semiconductor device 900, it is possible to guarantee the breakdown voltage of elements included in internal power supply utilizing circuit 907 of its main component, as well as to improve operating speed, and to reduce power dissipation.
FIG. 30 is a diagram schematically showing a configuration of the internal voltage down converter 905 shown in FIG. 29. In FIG. 30, internal voltage down converter 905 includes: a reference voltage generating circuit 910 for generating a reference voltage Vref at a constant voltage level from external power supply voltage EXV supplied to external power supply terminal 901; a comparison circuit 912 for comparing internal power supply voltage VCI on internal power supply line 906 with reference voltage Vref; and a drive element 914 formed of a p channel MOS transistor (insulated gate type field effect transistor) 914 for supplying a current from external power supply terminal 901 to internal power supply line 906 in accordance with an output signal of comparison circuit 912.
Comparison circuit 912 has a positive input receiving internal power supply voltage VCI, and a negative input receiving reference voltage Vref. Comparison circuit 912, which is normally composed of a differential amplifier, differentially amplifies internal power supply voltage VCI and reference voltage Vref. The operation of the internal voltage down converter shown in FIG. 30 will now be described in brief.
Reference voltage generating circuit 910 generates reference voltage Vref at a constant voltage level independent of external power supply voltage EXV. In the case where internal power supply voltage VCI on internal power supply line 906 is higher than this reference voltage Vref, the output of comparison circuit 912 is at an "H" level, and drive element 914 is in an OFF state. In this state, no current is supplied from external power supply terminal 901 to internal power supply line 906.
In contrast, when internal power supply voltage VCI is lower than reference voltage Vref, the output of comparison circuit 912 attains a low level in accordance with the difference between internal power supply voltage VCI and reference voltage Vref. Drive element 914 increased in its conductance supplies a current from external power supply terminal 901 to internal power supply line 906 to raise the voltage level of internal power supply voltage VCI. Internal power supply voltage VCI is kept at the voltage level of reference voltage Vref by a feedback loop formed of comparison circuit 912, drive element 914 and internal power supply line 906.
As explained above, since the voltage level of internal power supply voltage VCI is determined by reference voltage Vref, reference voltage Vref is required to have a small temperature dependency as well as a small dependency on external power supply voltage EXV within a prescribed range of the external power supply voltage EXV, from the standpoint of stable operation of internal power supply utilizing circuit 907 (see FIG. 40).
Such reference voltage is used in a variety of applications besides the above-described internal voltage down converter. For example, in an input circuit receiving an external signal and generating an internal binary signal, such reference voltage is used to determine logical levels of H level and L level of the external signal. In addition, in a memory device having no complementary type read data, such as a read only memory (ROM), the reference voltage is used in a circuit for reading and amplifying memory cell data to determine the H and L levels of the memory cell data.
The reference voltage is also utilized as a bias voltage of a constant current source element included in the differential amplifying circuit. This bias voltage of the constant current element determines a power supply current of the differential amplifying circuit as well as its response speed. Thus, the reference voltage is used both in digital and analog integrated circuits.
FIG. 31 shows a configuration of a conventional reference voltage generating circuit disclosed in Japanese Patent Laying-Open No. 2-67610, for example. Here, the reference voltage may be generated from any of an external power supply voltage or an internal power supply voltage. Thus, the power supply voltage in FIG. 31 is denoted by "Vcc" to include both external and internal power supply voltages.
In FIG. 31, the reference voltage generating circuit includes: an enhancement type p channel MOS transistor Q1 connected between a power supply node 1 and an output node 2 for supplying a current from power supply node 1 to output node 2 according to a voltage on a node 3; an enhancement type p channel MOS transistor Q2 connected between output node 2 and a ground node 4 and having its gate connected to ground node 4; an enhancement type p channel MOS transistor Q3 connected between power supply node 1 and node 3 for clamping the voltage on node 3 at a prescribed voltage level; and a resistance element 5 connected between node 3 and ground node 4 and having a resistance value R1.
MOS transistors Q1, Q2 and Q3 have threshold voltages VTP1, VTP2 and VTP3, respectively. MOS transistor Q3 has its gate and drain interconnected, and its backgate connected to power supply node 1. The backgate of MOS transistor Q1 is connected to power supply node 1, and the backgate of MOS transistor Q2 is connected to output node 2. The source and backgate of MOS transistor Q2 are adapted to have the same potential to eliminate backgate effects. The operation of reference voltage generating circuit shown in FIG. 31 will now be described.
Now, conductance factors .beta. of MOS transistors Q1, Q2 and Q3 are expressed as .beta.1, .beta.2 and .beta.3, and the voltage on node 3 as V3. Here, conductance factor .beta. is a constant that is proportional to the ratio between channel width W and channel length L. Assuming that MOS transistors Q1 to Q3 all operate in a saturation region, a drain current IDS flowing through MOS transistors Q1 and Q2 when the voltage on power supply node 1 is Vcc can be expressed by the following equation. ##EQU1## where Vo represents an output voltage at output node 2. In the case where resistance value R1 of resistance element 5 is sufficiently large relative to an equivalent resistance value (ON resistance) of MOS transistor Q3, MOS transistor Q3 operates in a diode mode, and the voltage V3 of node 3 is expressed by the following equation. ##EQU2## In the above equation (2), the third term on the right side represents contribution of channel resistance component of MOS transistor Q3. The equation (2) is derived from an equation for calculating the voltage of node 3 from a drain current of MOS transistor Q3 operating in a saturation region and resistance element 5. In the approximate expression, resistance value R1 of resistance element 5 is sufficiently large, so that the term 1/R1.multidot..beta.3 is neglected. The voltage Vo generated on output node 2 is obtained by the following equation from equations (1) and (2). ##EQU3##
As seen from this equation (3), output voltage Vo is determined by threshold voltages VTP1 to VTP3 of respective MOS transistors Q1 to Q3, conductance factors .beta.1 to .beta.3 of respective MOS transistors Q1 to Q3, and resistance value R1 of resistance element 5. As shown in the third term in the first term of this equation (3), however, power supply voltage Vcc is included as a determining factor, and therefore, output voltage Vo depends on this power supply voltage Vcc on power supply node 1 to some extent.
More specifically, as shown in FIG. 32, output voltage Vo increases as power supply voltage Vcc increases. Even when reaching a fixed value, however, power supply voltage Vcc does not stabilize at that fixed value as shown with a dotted line in FIG. 32, but continues to increase in accordance with the increase of power supply voltage Vcc. If this output voltage Vo is used as a reference voltage for generating the above-described internal power supply voltage, there arise problems that the internal power supply voltage will change dependent on the change in the external power supply voltage, and that the operation timing in the internal circuits will vary (due to the increase in operating speed of MOS transistors being components thereof), which leads to decrease in operating margin of the internal circuits.
In addition to the above-described problems related to the power supply voltage dependency of the output voltage, there is another problem that is attributable to temperature dependency of the threshold voltage of MOS transistor. More specifically, as shown in FIG. 33, the threshold voltage VTN of n channel MOS transistor decreases as temperature T increases, and conversely, the threshold voltage VTP of p channel MOS transistor increases (i.e., the absolute value becomes smaller) according to the increase of temperature T. Note that, in FIG. 33, the abscissa represents temperature T, and the ordinate represents voltage value V.
Reviewing the above equation (3) from the standpoint of the temperature dependency of threshold voltage, a difference between threshold voltages VTP1 and VTP3 is obtained in the first term on the right side, and the temperature dependencies of these threshold voltages VTP1 and VTP3 are canceled. In the third term of the first term on the right side, however, there exists threshold voltage VTP3. In the second term on the right side of equation (3), threshold voltage VTP2 exists. Since these threshold voltages VTP3 and VTP2 are different in order, their temperature dependencies are not canceled, and thus, the temperature dependency of the threshold voltage VTP2 significantly appears on output voltage Vo. That is, the output voltage Vo has temperature dependency mainly attributable to the temperature dependency of threshold voltage VTP2. Therefore, there arises a problem that output voltage Vo from this reference voltage generating circuit changes according to the change of operating environment (operating temperature and power supply voltage), and thus, it is impossible to generate a reference voltage that can be held constantly at a stable, fixed level.
In practical use, this output voltage can be used in some cases even when it exhibits some dependency on power supply voltage or temperature. However, such power supply voltage or temperature dependency of output voltage Vo is preferred to be as small as possible such that an internal circuit can stably operate in the event of fluctuation of power supply voltage Vcc or temperature.